On-line built-in test (BIT) equipment is generally known; however, such apparatus is now becoming a vital part of digital systems, such as computers, which are comprised of many interconnected modules, each containing a plurality of large scale integration semiconductor chips which operate, for example, as individual signal processing units. Due to the chip complexity, reliability and pinout capability present in currently utilized large scale integrated (LSI) chips, many different types of constraints are imposed on system design and any built-in test hardware must maintain a very low profile from an overall system viewpoint. By this is meant maximum failure information must be extracted at a minimum cost in hardware and connectivity.
Accordingly, current built-in test equipment for digital systems is normally limited to the detection of occurrences and the conveyance of an error alarm to a system level control. To avoid added hardware and/or signal paths, little or no detailed information is normally conveyed from the site of the observed failure to higher system levels and separate software and/or hardware is relied upon to identify the error source.